PA-RISC 2.0 Architecture

Series
Prentice Hall
Author
Gerry Kane / Hewlett-Packard Professional Books  
Publisher
Prentice Hall
Cover
Softcover
Edition
1
Language
English
Total pages
496
Pub.-date
December 1995
ISBN13
9780131827349
ISBN
0131827340
Related Titles


Product detail

Product Price CHF Available  
9780131827349
PA-RISC 2.0 Architecture
61.30 approx. 7-9 days

Description

For system designers and analysts, system software programmers, application developers, and technical managers.

Hewlett-Packard's PA-RISC architecture is one of the most mature Reduced Instruction Set Computer designs in the industry. This book is the first publicly available, detailed description of the next revision of the PA-RISC architecture. Covers the RISC characteristics of PA-RISC, PA-RISC processing resources, addressing and access control, control flow, interruptions, and an overview of the instruction set and floating point corprocessor.

Features

  • details the key features of PA-RISC that differentiates it from other RISC architectures: pathlength reduction features, integrated CPU features, and extendibility and longevity features.
  • explains the "precision architecture" approach of PA-RISC that enables the implementation of PA-RISC machines that are significantly more efficient than competing RISC machines.

Table of Contents



1. Overview.

Traditional RISC Characteristics of PA-RISC. PA-RISC-The Genius is in the Details. A Critical Calculus: Instruction Pathlength. Multimedia Support: The Precision Process Illustrated. Integrated CPU. Extensibility and Longevity. System Organization.



2. Processing Resources.

Non-Privileged Software-Accessible Registers. Privileged Software-Accessible Registers. Unused Registers and Bits. Data Types. Byte Ordering (Big Endian/Little Endian).



3. Addressing and Access Control.

Physical and Absolute Addressing. Virtual Addressing. Pointers and Address Specification. Address Resolution and the TLB. Access Control.



4. Page Table Structure.

Caches. Control Flow. Branching. Nullification. Instruction Execution. Instruction Pipelining.



5. Interruptions.

Interrupt Classes. Interruption Handling. Instruction Recoverability. Masking and Nesting of Interruptions. Interruption Priorities. Return from Interruption. Interruption Descriptions.



6. Instruction Set Overview.

Computation Instructions. Multimedia Instructions. Memory Reference Instructions. Long Immediate Instructions. Branch Instructions. System Control Instructions. Assist Instructions. Conditions and Control Flow. Additional Notes on the Instruction Set.



7. Instruction Descriptions.


8. Floating-point Coprocessor.

The IEEE Standard. The Instruction Set. Coprocessor Registers. Data Registers. Data Formats. Floating-Point Status Register. Floating-Point Instruction Set.



9. Floating-Point Instruction Set.


10. Floating-Point Exceptions.

Exception Registers. Interruptions and Exceptions. Saving and Restoring State.



11. Performance Monitor Coprocessor.

Performance Monitor Instructions. Performance Monitor Interruptions. Monitor Units.



Glossary.


Appendix B. Instruction Formats.


Appendix C. Operation Codes.


Appendix D. Conditions.


Appendix E. Instruction Notation Control Structures.


Appendix F. TLB and Cache Control.


Appendix G. Memory Ordering Model.


Appendix H. Address Formation Details.


Appendix I. Programming Notes.


Appendix J. PA-RISC 2 Instruction Completers & Pseudo-Ops.