Starter's Guide to Verilog 2001

Series
Prentice Hall
Author
Michael D. Ciletti  
Publisher
Pearson
Cover
Softcover
Edition
1
Language
English
Total pages
256
Pub.-date
September 2003
ISBN13
9780131415560
ISBN
0131415565
Related Titles



Description

For undergraduate courses in Advanced Digital Logic and Advanced Digital Design in departments of electrical engineering, computer engineering, and computer science.

Introducing the Verilog HDL in a brief format, this text presents a selected set of the changes the popular hardware underwent in its first revision-emerging as IEEE Std 1364-2001 or Verilog-2001. It addresses the main features that support the design of combinational and sequential logic, and emphasizes synthesizable models, with a limited discussion of the theoretical framework for synthesis.

Features

  • Focus on modern digital design methodology.
  • Brief but comprehensive presentation.
    • Covers the design of finite-state machines to control datapaths.

  • Student-friendly format-Features special icons throughout.
    • Highlights modeling tips and features of Verilog 2001.

  • Thorough treatment of behavioral modeling-Demonstrates the utility of ASM and ASMD charts for behavioral modeling.
  • Numerous graphical illustrations.
    • Clarifies concepts and enhances students' understanding of them.

  • Chapter-end problems and 100 verified examples throughout-Supported by ongoing website containing source files of all models developed with examples.
    • Gives students opportunity to practice and apply what they have learned, and provides them with an indexed list of all models developed in the examples.

Table of Contents



1. Introduction to Digital Design Methodology.


2. Basic Concepts: Primitives, Data Types, and Operators in Verilog.


3. Modeling Structure with Verilog.


4. Modeling Behavior with Verilog.


5. Modeling Finite-State Mechanics and Datapath Controllers with Verilog.


Appendices.