|Digital Design: Principles and Practices||
Digital Design: Principles and Practices
|287.50||approx. 7-9 days|
For courses in digital design
Establishing a solid foundation of digital design principles
An authoritative introduction to basic digital design, Digital Design: Principles and Practices helps students build a foundational understanding of theoretical and engineering principles. This book gives students the opportunity to learn the basics at the high level (HDLs), at the low level (electrical circuits), and throughout the “vast middle” (gates, flip-flops, and higher-level digital-design building blocks). The author’s 30 years of experience in both industrial and university settings brings weight and credibility to the material, and with broad coverage of logic design practices, the 5th Edition gives students a look at how digital design works in the real world.
Principles and practices theme
Features for student success
About the Book
• Verilog coverage only; there’s no VHDL.
• Contains many more HDL examples and a much greater emphasis on design flow and on test benches, including purely stimulative as well as self-checking ones.
• TTL, SSI, MSI, 74-series logic, PLDs, and CPLDs have been deprecated.
• Karnaugh-map-based minimization has been minimized.
• A greater emphasis on FPGA-based design, FPGA architectural features, and synthesis results and trade-offs.
• To make the book more accessible to non-EE computer engineering students, detailed coverage of CMOS circuits has been moved to Chapter 14 and a minimal amount of electronics has been added to Chapter 1 so that the CMOS chapter can be skipped entirely if desired.
• Verilog concepts are interspersed in sidebars in Chapters 6 and 7 while retaining a comprehensive Verilog tutorial and reference in Chapter 5.
• The chapter on combinational-logic elements has been split into three, to facilitate going straight to state machines after just the first if desired. This also allows more coverage of arithmetic circuits in the last.
• An entire chapter has been devoted to state-machine design in Verilog, including many examples.
• The chapter on synchronous design methodology now contains a detailed control-unit-plus-datapath example and a comprehensive example on crossing clocking domains using asynchronous FIFOs.